1. Field of the Invention
This invention relates to a digital memory circuit and, more particularly, to a circuit for non-destructive reading of a variable threshold insulated gate field effect memory transistor.
2. Description of the Prior Art
Variable threshold transistors that display memory characteristics are known in the prior art. For example, U.S. Pat. No. 3,508,211 entitled "Electrically Alterable Non-Destructive Readout Field Effect Transistor Memory" and assigned to the present assignee, relates to a variable threshold transistor useful as a memory element. Each element is comprised of a variable threshold insulated gate field effect transistor whose conduction threshold is electrically alterable by impressing a binary WRITE voltage between the gate electrode and the substrate in excess of a predetermined finite magnitude. The polarity of the WRITE voltage, moreover, determines the sense in which the threshold is varied. Furthermore, by application of a fixed interrogation voltage or READ voltage, having a value intermediate to the binary value conduction thresholds, to the gate electrode the binary condition of the transistor can be sensed, for example, by monitoring the magnitude of the resulting source to drain current. The value of the variable threshold transistor memory element lies partly in the fact that it is completely compatible with the use of integrated microelectronic circuit fabrication techniques in devices useful in digital computers.
Generally, the magnitude of the interrogation or READ voltage is small and insufficient to substantially change the pre-existing conduction threshold so that essentially a non-destructive readout is achieved. However, in certain systems there is a need for interrogation of the memory transistor device many millions of times before the initiation of a new WRITE signal. In such a system the disturb voltage, produced as a result of the READ voltage, although small for a relatively few READ cycles, may eventually destroy the memory of the device before a new WRITE cycle is or may be employed. Furthermore, during READ voltage interrogation of the memory device, the disturb voltage varies in magnitude and polarity as a function of the threshold voltage of the memory device, which in turn is disturbed by the disturb voltage. Accordingly, it is extremely difficult to calculate the interrogation cycle lifetime of the memory device without actually interrogating the device throughout its lifetime, i.e., until memory destruction. Furthermore, the memory retention of the device also depends upon the inherent qualities of the device and the interrogation scheme used to sense the data of the device. Sensing schemes, moreover, which have been employed to determine the binary value of the memory cells have also applied an additional disturb potential to the memory device which likewise decreases the retention lifetime of the device. Accordingly, it is necessary to provide a memory device, which is to retain operable and valid data after being subjected to a relatively large number of interrogation cycles, with a highly non-destructive interrogation scheme and sensing scheme.